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DAC Jitter Modeling for CTSD Modulator

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RamyRady_RF

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Hello,

I was implementing a 5 bit DAC to be used in a CT sigma delta modulator. I would like to model the error due to clk Jitter at the output of the DAC in VerilogA. Any Ideas?
 

Hi,

Do you know How to add mismatch to the DAC Model that calculates the value each clock?

Thanks
 

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