alexandicity
Newbie level 6
Signal ignoring initializers and initializing to random state
Hi all!
I have a VHDL program that, despite all my effort to stop it, keeps initializing its signals in a random state. Sort of: it apparently initializes in the same state on each powerup, but the pattern that comes up I don't recognize. This initialization state appears to change on each reprogramming event to a new random pattern that will be consistent across all restarts.
Take, for example, a signal vector I have, reg_control. My problem appears to affect all my signals, but I use this one as an illustration due to its relative simplicity. I declare it as follows:
I understand that that initialiser is used in simulation only, and that it is disregarded in hardware. I have no combinational logic that drives this vector, but instead it is manipulated in a PROCESS:
In the above, the first part before the ELSE is trying to force assignment to all zeros, which is what I want it to start at, by repeatedly setting it to zero for a short while after startup - which I expect would be implemented in the hardware. The second part, after the ELSE, contains the only two situations in my VHDL where the vector is assigned a non-zero value, although neither of the conditions are ever true in this test case (when the conditions are true, I do see these assignments working properly). The assignment to X"0000" works fine. There are no other deliberate assignments to a non-zero value, so I am uncertain how these signals keep getting set to anything other than zero.
The value in this vector is assigned into other signals and ports in many places in combinational and sequential areas of the code, but such read operations, I would hope, would not cause assignment of this vector! One of these combinational assignments is to output pins; it is here that I can see that the signal vector is not all-zero.
The target device is a ProASIC3, and I am using Libero SoC. I'm fairly new to FPGA development, so it's entirely possible there's some setting or configuration outside of the VHDL that I've not seen. But more likely, I suspect I've not implemented in VHDL a correct method of assigning this vector to all zeros until otherwise assigned - can anyone see why this might be? Is there a best-practice way to assign a signal a value "at startup" until it is given a new value by an assignment in a PROCESS block?
Thank you!
Hi all!
I have a VHDL program that, despite all my effort to stop it, keeps initializing its signals in a random state. Sort of: it apparently initializes in the same state on each powerup, but the pattern that comes up I don't recognize. This initialization state appears to change on each reprogramming event to a new random pattern that will be consistent across all restarts.
Take, for example, a signal vector I have, reg_control. My problem appears to affect all my signals, but I use this one as an illustration due to its relative simplicity. I declare it as follows:
Code:
architecture Top_Level_Arch of Top is
...
signal [B]reg_control[/B]: std_logic_vector(1 to 16) := X"0000";
...
I understand that that initialiser is used in simulation only, and that it is disregarded in hardware. I have no combinational logic that drives this vector, but instead it is manipulated in a PROCESS:
Code:
PROCESS(clk)
VARIABLE reset_count : INTEGER :=0;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (reset_count < 10000000) THEN
-- Reset hold-off for 200ms at 50MHz
reset_count := reset_count + 1;
[B]reg_control [/B]<= X"0000";
ELSE
...
IF (some_condition) THEN
[B]reg_control[/B](to_integer(unsigned(bit_to_set))) <= '1';
END IF;
IF (some_other_condition) THEN
[B]reg_control [/B]<= X"FFFF";
END IF;
IF (Yet_another_condition) THEN
[B]reg_control [/B]<= X"0000";
END IF;
...
In the above, the first part before the ELSE is trying to force assignment to all zeros, which is what I want it to start at, by repeatedly setting it to zero for a short while after startup - which I expect would be implemented in the hardware. The second part, after the ELSE, contains the only two situations in my VHDL where the vector is assigned a non-zero value, although neither of the conditions are ever true in this test case (when the conditions are true, I do see these assignments working properly). The assignment to X"0000" works fine. There are no other deliberate assignments to a non-zero value, so I am uncertain how these signals keep getting set to anything other than zero.
The value in this vector is assigned into other signals and ports in many places in combinational and sequential areas of the code, but such read operations, I would hope, would not cause assignment of this vector! One of these combinational assignments is to output pins; it is here that I can see that the signal vector is not all-zero.
The target device is a ProASIC3, and I am using Libero SoC. I'm fairly new to FPGA development, so it's entirely possible there's some setting or configuration outside of the VHDL that I've not seen. But more likely, I suspect I've not implemented in VHDL a correct method of assigning this vector to all zeros until otherwise assigned - can anyone see why this might be? Is there a best-practice way to assign a signal a value "at startup" until it is given a new value by an assignment in a PROCESS block?
Thank you!