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[SOLVED] Integrator Reset in Verilog -A

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ashrafsazid

ashrafsazid

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Hi, I want to reset the output of an Integrator. I used this verilog code for integration purpose:

Code: 
analog begin
if (V(reset) > 0) begin
	V(out) <+  gnd;
end else if ( V(reset) == 0) begin
	V(out)	<+  vout;
	end
	vout	=   idtmod(V(in), 0);

end

Capture.PNG

The problem is when reset is active it indeed goes to gnd=0, but later starts again from that previous position, I want the inegrator will start from gnd again after reset is low.

Please help me.
 
Last edited by a moderator:

First, can you understand difference between idt() and idtmod() ?

Second, can you understand arguments of idt() and idtmod() ?
 

actually i tried with idt also, 0 means from initial timing on the second arguments. there is also another argument 'assert'. i just want to integrate from the time when reset becomes zero, can you please help me out?
 

ashrafsazid said:
actually i tried with idt also,
0 means from initial timing on the second arguments.
there is also another argument 'assert'.
Click to expand...
Simply use 'assert'.

Asynchronous Reset.

Code: 
`include "disciplines.vams"
`include "constants.vams"

module hoge(in, out, reset);
inout in, out, reset;
electrical in, out, reset;

parameter real vth = 0.5;

integer assert;

analog begin
   @(initial_step) assert = 0;

   if(V(reset) >= vth)
      assert = 1;
   else
      assert = 0;

   V(out) <+ idt(V(in), 0.0, assert);
end //analog

endmodule
 
Last edited:
Thanks Man! You are great! So that means where assert becomes 0 it will start integrating from there, right? If possible, please give me a small description how assert works.
 

ashrafsazid said:
So that means where asserts become 1 it will start integrating from there, right?
Click to expand...
No.
Integration starts at time=0 and falling edge of V(reset).

Code: 
`include "disciplines.vams"
`include "constants.vams"

module hoge(in, out, reset);
inout in, out, reset;
electrical in, out, reset;

parameter real vth = 0.5;

integer assert;

analog begin
   @(initial_step) assert = 0;

   @( cross(V(reset)-vth, 1) )  assert = 1;
   @( cross(V(reset)-vth, -1) ) assert = 0;

   //assert = V(reset) >= vth;
 
   V(out) <+ idt(V(in), 0.0, assert);
end //analog

endmodule
 
Last edited:

Thanks, Now I understand the statement from your code and cadence verilog-A manual. Actually there was no useful example on the manual, only this description

assert.PNG

Thank you very much! you help me always.
 

ashrafsazid said:
Thanks, Now I understand the statement from your code and cadence verilog-A manual. Actually there was no useful example on the manual, only this description
Click to expand...
See "ahdlLib", "pllLib", "pllMMLib", "rfLib" and "bmslib" shipped with Cadence dfII.
You can find many examples.
 
what if I want to integrate the signal only at clk=1? I mean I want to use a clk, and integrate only clk on high.
 

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