FlyingDutch
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Hello,
I would like to ask one question concerning conditional adding VHDL/Verilog modules to "ISE Webpack" project. I would like to achvieve similiar effect like using C language pre-processor to define symbol and adding code to compilation based on this symbol value. I mean something like this (in C language):
I need such feature for debbuging purpose of VHDL project. I have external LCD display connected to my FPGA circiut by UART. In debbuging mode I want have possibility of sending messages to display from FPGA. In "Release" mode I don't need modules implementing UART on FPGA side to economize resources using.
Could someone of more experienced colleagues point me a solution to my problem
or give me a hint where to look for ?
Kind Regards
I would like to ask one question concerning conditional adding VHDL/Verilog modules to "ISE Webpack" project. I would like to achvieve similiar effect like using C language pre-processor to define symbol and adding code to compilation based on this symbol value. I mean something like this (in C language):
Code:
#define DEBUG
...
...
...
#ifdef DEBUG
# include <stdio.h>
std::cout << "[RE_words] " << re << std::endl;
... further code to include and compilation
#endif
I need such feature for debbuging purpose of VHDL project. I have external LCD display connected to my FPGA circiut by UART. In debbuging mode I want have possibility of sending messages to display from FPGA. In "Release" mode I don't need modules implementing UART on FPGA side to economize resources using.
Could someone of more experienced colleagues point me a solution to my problem
or give me a hint where to look for ?
Kind Regards