alexander3318
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Hi, all,
I'm learning the layout design, when I do the DRC check, I received the error:
GR999: RX must be within CHIPEDGE>=0.00 um
GR999: M1 must be within CHIPEDGE>=0.00 um
GR999a: PC must be within CHIPEDGE>=0.00 um
GR999a: NW must be within CHIPEDGE>=0.00 um
It seems that every layer should be inside the chip edge. However, I don't know how to define the chip edge, any one can help me with this?
I'm learning the layout design, when I do the DRC check, I received the error:
GR999: RX must be within CHIPEDGE>=0.00 um
GR999: M1 must be within CHIPEDGE>=0.00 um
GR999a: PC must be within CHIPEDGE>=0.00 um
GR999a: NW must be within CHIPEDGE>=0.00 um
It seems that every layer should be inside the chip edge. However, I don't know how to define the chip edge, any one can help me with this?