Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

using if statement in verilog

Status
Not open for further replies.

emerson_11

Member level 2
Joined
Jan 23, 2016
Messages
44
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
355
I am getting a 50bit signed number result from my multiplier. Now based on the sign bit my output would be classified either o or 1. I have written the verilog code as such Capture.JPG but I am receiving such error. Could anyone guide me?
 

You want to put this into an always block, or just have an assignment with a ternary operator, or just assign class to the bit at index 49.

This is attempting to use the if-generate structure, which conditionally includes logic at synthesis time based on constant values. I didn't realize you could skip "generate" but Verilog is fairly relaxed on syntax rules.
 
  • Like
Reactions: dpaul

    dpaul

    Points: 2
    Helpful Answer Positive Rating
could you correct me the code that i have made error in the screenshot ?
 

Look like your are writing Verilog with a software coding style. Check again how to write verilog if/else construct.

With that logic, you can imagine a wire which use to connect svm[49] to class directly.
It can be archieve by simple assignment.
 

Why are you make it overcomplicated? Why not:

assign class = svm[49];
 

When svm[49] is HIGH, then class has value 1b'1, else it has value 1b'0. As you have defined no sensitivity list so I would write it as...
assign class = (svm[49]) ? 1b'1 : 1b'0;
 

assign class = (svm[49]) ? 1b'1 : 1b'0;

There is no point of checking the bit 49, class can be assigned to its value straight away. As simple as:
assign class = svm[49];
 

If you don't want to learn then birbal has your answer,
else
If you want to learn then know this

assign
Continuous assignments are the most basic assignment in dataflow modelling. Continuous assignments are used to model in combinational logic. It drives values into the nets.

In vhdl think of this as

Code VHDL - [expand]
1
2
3
4
-- a mux/switch
x <= a when b else c;
-- constant assign
y <= consant



Whereas in Verilog

Code Verilog - [expand]
1
2
3
4
// mux or switch
assign x = b ? a : c;
// constant assignment
assign y = somevalue;



What you implemented was a sequential if, with combinatorial assign. In that method you'd need a

Code Verilog - [expand]
1
2
3
4
always @ *
begin
  if b==1 x = a; else x=c; //Verilog uses begin and end as c language { }
end



VGoodtimes said as much, but he's such an expert that he uses expert speak - like ternary (?:) operations
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top