pwq1999
Member level 2
modelsim expanded time
i write test bench using verilog,my input signals change at the same time with the rising edge of clock. now question is , my clock's rising edge detect the signals' value which is after the clock's rising edge, but i think the input signals' value should be before the the clock's rising edge.
any tricks can be suggested when simulating with modelsim ?
thanks!
i write test bench using verilog,my input signals change at the same time with the rising edge of clock. now question is , my clock's rising edge detect the signals' value which is after the clock's rising edge, but i think the input signals' value should be before the the clock's rising edge.
any tricks can be suggested when simulating with modelsim ?
thanks!