chandlerbing65nm
Member level 5
I'm having difficulty in understanding the VHDL template for FIFO my instructor gave to me. Below is the instruction:
So, there are no flags in this template. There should be no edit in the port list and signal/variable list.
Could anyone please give me information about how to use these in the code:
Seems to me that
I have an idea in mind how to code this problem but not really sure if I'm correct especially the
Using VHDL, Design a FIFO memory. Make it 8-deep, 9 bits wide. When a read signal is asserted, the output of the FIFO should be enabled, otherwise it should be high impedance. When the write signal is asserted, write to one of the 9 bit registers. Use RdInc and WrInc as input signals to increment the pointers that indicate which register to read or write. Use RdPtrClr and WrPtrClr as input signals which reset the pointers to point to the first register in the array. Do not implement full or empty signals.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FIFO8x9 is
port(
clk, rst: in std_logic;
RdPtrClr, WrPtrClr: in std_logic;
RdInc, WrInc: in std_logic;
DataIn: in std_logic_vector(8 downto 0);
DataOut: out std_logic_vector(8 downto 0);
rden, wren: in std_logic
);
end entity FIFO8x9;
architecture RTL of FIFO8x9 is
--signal declarations
type fifo_array is array(7 downto 0) of std_logic_vector(8 downto 0); -- makes use of VHDL’s enumerated type
signal fifo: fifo_array;
signal wrptr, rdptr: unsigned(2 downto 0);
signal en: std_logic_vector(7 downto 0);
signal dmuxout: std_logic_vector(8 downto 0);
begin
So, there are no flags in this template. There should be no edit in the port list and signal/variable list.
Could anyone please give me information about how to use these in the code:
RdPtrClr -- Read Pointer Clear, to reset the read pointer
WrPtrClr -- Write Pointer Clear, to reset the write pointer
rdinc -- Read pointer increment signal
wrinc -- Write pointer increment signal
Seems to me that
is the incremental element, i.e en <= en + 1.signal en: std_logic_vector(7 downto 0);
I have an idea in mind how to code this problem but not really sure if I'm correct especially the
. How could I use this?signal wrptr, rdptr: unsigned(2 downto 0);
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