Cesar0182
Member level 5
greetings ... tell you that I am very new to systemverilog and I have some files to perform a simulation test for a project. This test has a main file stimulus.sv which creates an instance of another called local_g1_test_bench.sv, in this second file a vector is created for the differential clock that will be used in different modules, as follows.
I want to create the differential clock vector in the stimulus.sv file and send it to local_g1_test_bench.sv as a parameter. Could someone help me with some information to do this, please.
I leave attached the files stimulus.sv and local_g1_test_bench.sv
Code:
reg sim_pim1_uclock0 = 1;//IEA Added
reg sim_pim1_uclock1 = 1;//IEA Added
reg sim_pim1_uclock2 = 1;//IEA Added
reg sim_pim1_uclock3 = 1;//IEA Added
always//IEA Added
#2500 sim_pim1_uclock0 = ~sim_pim1_uclock0; // 6.80 nS period 147.06 MHz NEW//IEA Added
always//IEA Added
#2500 sim_pim1_uclock1 = ~sim_pim1_uclock1; // 6.80 nS period 147.06 MHz NEW//IEA Added
always//IEA Added
#2500 sim_pim1_uclock2 = ~sim_pim1_uclock2; // 6.80 nS period 147.06 MHz NEW//IEA Added
always//IEA Added
#2500 sim_pim1_uclock3 = ~sim_pim1_uclock3; // 6.80 nS period 147.06 MHz NEW//IEA Added
//assign i_pim1_uclk_p = {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
//assign i_pim1_uclk_n = ~i_pim1_uclk_p;
wire [3:0] pgm_user_clk_p = {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
wire [3:0] pgm_user_clk_n = ~pgm_user_clk_p;
I want to create the differential clock vector in the stimulus.sv file and send it to local_g1_test_bench.sv as a parameter. Could someone help me with some information to do this, please.
I leave attached the files stimulus.sv and local_g1_test_bench.sv