engr_joni_ee
Advanced Member level 3
Hi,
I am considering AD9257 ADC for my application. The ADC chip is octal which means 8 ADC on chip. The resolution is 14 bits and sampling rate is 65 MSPS. Each channel has serial LVDS output. There is a statement on the first page of the datasheet which reads.
"Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 455 MHz and supports double data rate (DDR) operation."
I guess the differential output means that positive data DA+ and negative data DA- from channel A are just inverted in polarity otherwise they are same, right ? and the double data rate sampling means that it is possible to sample at both edges, right ? which means that (65 x 14) /2 = 455 MHz is the data bit clock to FPGA, right ? and the PCB layout has to be in accordance with 455 MHz, and not 910 MHz, right ?
I am considering AD9257 ADC for my application. The ADC chip is octal which means 8 ADC on chip. The resolution is 14 bits and sampling rate is 65 MSPS. Each channel has serial LVDS output. There is a statement on the first page of the datasheet which reads.
"Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 455 MHz and supports double data rate (DDR) operation."
I guess the differential output means that positive data DA+ and negative data DA- from channel A are just inverted in polarity otherwise they are same, right ? and the double data rate sampling means that it is possible to sample at both edges, right ? which means that (65 x 14) /2 = 455 MHz is the data bit clock to FPGA, right ? and the PCB layout has to be in accordance with 455 MHz, and not 910 MHz, right ?