ashueda
Newbie level 5
Hi all,
I am new to Active-HDL. I am starting to learn the tool by simulating a simple two input AND gate. The code is following,
and the testbench is the following,
but when i simulate the code i get no output for the signal out_c, i.e., no output,
please help me where I am wrong ??
I tried the same code in modelsim it is working OK, but why not active-hdl??
I have to work in active-hdl only for my project.
please help me, thanks in advance
thanks
I am new to Active-HDL. I am starting to learn the tool by simulating a simple two input AND gate. The code is following,
Code:
--and.vhd
entity and_gate is
port (A,B:in bit;C:out bit);
end and_gate;
architecture and_gate_ar of and_gate is
begin
C<=A and B;
end and_gate_ar;
and the testbench is the following,
Code:
--and_tbench.vhd
entity tb_en is
end tb_en;
architecture tb_ar of tb_en is
component and_gate
port(
A : in BIT;
B : in BIT;
C : out BIT
);
end component;
signal a_i,b_i:bit;
signal out_c:bit;
begin
stimulus: process
begin
a_i <= '0'; b_i <= '0';
wait for 100 ns;
a_i <= '0'; b_i <= '1';
wait for 100 ns;
a_i <= '1'; b_i <= '0';
wait for 100 ns;
a_i <= '1'; b_i <= '1';
wait for 100 ns;
if now = 400 ns then
wait;
end if;
end process stimulus;
add1 : and_gate port map(A => a_i, B => b_i, C => out_c);
end tb_ar;
but when i simulate the code i get no output for the signal out_c, i.e., no output,
please help me where I am wrong ??
I tried the same code in modelsim it is working OK, but why not active-hdl??
I have to work in active-hdl only for my project.
please help me, thanks in advance
thanks