Cesar0182
Member level 5
Greetings ... tell them that I am new using IP cores, and a couple of days ago they passed me a project (vhdl sources and IPs) where the IPs were made in Vivado 2013.4. I have managed to synthesize, simulate and implement this project without any problem in Vivado 2018.3 (no need to update the IPs) ... but now they asked me to update all the IPs of the project and again synthesize, simulate and implement the project. So far I have managed to update a large part of the IPs without affecting the operation of the project. But now I'm having problems updating Aurora 64B66B v9.1 to v11.2, because at the time of synthesizing I get the following errors that are shown in the attached image (synth_error).
I tried to comment the connections do_cc and reset, but I also get another error which is shown in the attached image (synth_error2).
Can someone please help me with this problem, thanks in advance.
I leave attached the Aurora IP that I am using without updating.
I tried to comment the connections do_cc and reset, but I also get another error which is shown in the attached image (synth_error2).
Can someone please help me with this problem, thanks in advance.
I leave attached the Aurora IP that I am using without updating.