kumatul123
Newbie level 2
Hi guys, I am stuck with key scheduling part in lightweight block PRESENT-80 on VHDL not sure how it generates the key in every itration following is a piece of code I am confuse lease help me out in this regard,,
please help me out how bit shuffeling is going over there.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 sbox0utput : present_sbox port map ( datainput => kinput(18 downto 15), dataoutput => koutput(79 downto 76) ); expand_process : process (kinput) is begin koutput(75 downto 0) <= kinput(14 downto 0) & kinput(79 downto 39) & (kinput(38 downto 34) xor std_logic_vector(to_unsigned(r_ctr, 5))) & kinput(33 downto 19); end process expand_process; end architecture rtl;
please help me out how bit shuffeling is going over there.