E
expertengr
Guest
What is the difference between the following VHDL Design Verifications.
1- Pre-synthesis VHDL Design Verification
2- Post-synthesis VHDL Design Verification
3- Post-layout VHDL Design Verification
The first (pre-synthesis) is very common and can be done by using ModelSim testbentch but how about the second and third ones ?
1- Pre-synthesis VHDL Design Verification
2- Post-synthesis VHDL Design Verification
3- Post-layout VHDL Design Verification
The first (pre-synthesis) is very common and can be done by using ModelSim testbentch but how about the second and third ones ?