shaiko
Advanced Member level 5
Hello,
In my design I have this very simple synchronous process:
IN_VALID_INFORMATION is a signal that's also generated synchronously - so I expect "counter_selected_read_burst" to increment one cycle AFTER it rises to '1'.
Unfortunately, this doesn't happen:
counter_selected_read_burst increments on the same edge as IN_VALID_INFORMATION rises from low to high.
What's going on??
I'm completely baffled.
In my design I have this very simple synchronous process:
Code:
counting_read_burst : process ( IN_CLOCK , IN_RESET_ASYNCHRONOUS ) is
begin
if IN_RESET_ASYNCHRONOUS = '1' then
counter_selected_read_burst <= ( others => '0' ) ;
elsif rising_edge ( IN_CLOCK ) then
if [COLOR="#FF0000"]IN_VALID_INFORMATION = '1'[/COLOR] then
if counter_selected_read_burst = selected_length_read_burst - 1 then
counter_selected_read_burst <= ( others => '0' ) ;
else
counter_selected_read_burst <= counter_selected_read_burst + 1 ;
end if ;
end if ;
end if ;
end process counting_read_burst ;
IN_VALID_INFORMATION is a signal that's also generated synchronously - so I expect "counter_selected_read_burst" to increment one cycle AFTER it rises to '1'.
Unfortunately, this doesn't happen:
counter_selected_read_burst increments on the same edge as IN_VALID_INFORMATION rises from low to high.
What's going on??
I'm completely baffled.