matrixofdynamism
Advanced Member level 2
I have come across the idea of "A Structured VHDL Design Method" by Jiri Gaisler. It basically proposes a certain style of describing hardware using VHDL in which we always split the hardware block into two processes, one is (mostly) written using variables and assigns the result into a signal, this process looks like a sequential C program; the other processes is clocked and updates signals inside it using the results from the other first process.
The basic idea is to make it easier to write complex algorithmic code in VHDL. Is this method known/used by anyone on this forum before?
The basic idea is to make it easier to write complex algorithmic code in VHDL. Is this method known/used by anyone on this forum before?