pbernardi
Full Member level 3
Hello All,
I was going to use an Spartan-7 device on my new project, but some colleagues were arguing to keep with current Spartan-6 due code compatibility reasons.
So, I my first idea was to make a synthesis of some codes we have for comparison, and I am reaching the conclusion that the Spartan-7 (and family 7 in general) is less efficient from logic point of view than Spartan-6? It seems odd to me.
Conditions and comments:
- I will not use any unique feature from 7 series family (ADC for example)
- Power and maximum speed are not so relevant here, only logic use.
- Of course, the code I use was developed for Spartan-6, so it might happen that they are optimized for 6-family, but still.
- They have different environment (ISE 14.7 x Vivado 2017.3)
- Seems that Artix-7/Spartan-7 have similar behavior regarding logic usage.
- There are differences specially related to the Block RAM size, I'm aware of that.
For example, a reference project (did not fix the I/O pins, balanced optimization in both cases):
For Spartan 6, using XC6SLX75-2CSG484:
Device Utilization Summary:
For Artix-7, using a XC7A75tcsg324-2:
Both uses the same code, but Spartan/Artix-7 has a worse logic usage in general, specially when taking into account the LUT usage. Has anyone here made similar investigation?
I was going to use an Spartan-7 device on my new project, but some colleagues were arguing to keep with current Spartan-6 due code compatibility reasons.
So, I my first idea was to make a synthesis of some codes we have for comparison, and I am reaching the conclusion that the Spartan-7 (and family 7 in general) is less efficient from logic point of view than Spartan-6? It seems odd to me.
Conditions and comments:
- I will not use any unique feature from 7 series family (ADC for example)
- Power and maximum speed are not so relevant here, only logic use.
- Of course, the code I use was developed for Spartan-6, so it might happen that they are optimized for 6-family, but still.
- They have different environment (ISE 14.7 x Vivado 2017.3)
- Seems that Artix-7/Spartan-7 have similar behavior regarding logic usage.
- There are differences specially related to the Block RAM size, I'm aware of that.
For example, a reference project (did not fix the I/O pins, balanced optimization in both cases):
For Spartan 6, using XC6SLX75-2CSG484:
Device Utilization Summary:
Code:
Slice Logic Utilization:
Number of Slice Registers: 980 out of 93,296 1%
Number used as Flip Flops: 980
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 4,404 out of 46,648 9%
Number used as logic: 4,051 out of 46,648 8%
Number using O6 output only: 3,097
Number using O5 output only: 206
Number using O5 and O6: 748
Number used as ROM: 0
Number used as Memory: 335 out of 11,072 3%
Number used as Dual Port RAM: 268
Number using O6 output only: 108
Number using O5 output only: 16
Number using O5 and O6: 144
Number used as Single Port RAM: 65
Number using O6 output only: 1
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 18
Number with same-slice register load: 1
Number with same-slice carry load: 17
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,597 out of 11,662 13%
Number of MUXCYs used: 560 out of 23,324 2%
Number of LUT Flip Flop pairs used: 4,554
Number with an unused Flip Flop: 3,703 out of 4,554 81%
Number with an unused LUT: 150 out of 4,554 3%
Number of fully used LUT-FF pairs: 701 out of 4,554 15%
Number of slice register sites lost
to control set restrictions: 0
For Artix-7, using a XC7A75tcsg324-2:
Code:
1. Slice Logic
--------------
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs | 5402 | 0 | 47200 | 11.44 |
| LUT as Logic | 5178 | 0 | 47200 | 10.97 |
| LUT as Memory | 224 | 0 | 19000 | 1.18 |
| LUT as Distributed RAM | 224 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 3207 | 0 | 94400 | 3.40 |
| Register as Flip Flop | 3207 | 0 | 94400 | 3.40 |
| Register as Latch | 0 | 0 | 94400 | 0.00 |
| F7 Muxes | 961 | 0 | 31700 | 3.03 |
| F8 Muxes | 132 | 0 | 15850 | 0.83 |
+----------------------------+------+-------+-----------+-------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+------+-------+-----------+-------+
| Slice | 2173 | 0 | 15850 | 13.71 |
| SLICEL | 1502 | 0 | | |
| SLICEM | 671 | 0 | | |
| LUT as Logic | 5178 | 0 | 47200 | 10.97 |
| using O5 output only | 0 | | | |
| using O6 output only | 4686 | | | |
| using O5 and O6 | 492 | | | |
| LUT as Memory | 224 | 0 | 19000 | 1.18 |
| LUT as Distributed RAM | 224 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 128 | | | |
| using O5 and O6 | 96 | | | |
| LUT as Shift Register | 0 | 0 | | |
| LUT Flip Flop Pairs | 575 | 0 | 47200 | 1.22 |
| fully used LUT-FF pairs | 150 | | | |
| LUT-FF pairs with one unused LUT output | 416 | | | |
| LUT-FF pairs with one unused Flip Flop | 417 | | | |
| Unique Control Sets | 339 | | | |
+-------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 13 | 0 | 105 | 12.38 |
| RAMB36/FIFO* | 8 | 0 | 105 | 7.62 |
| RAMB36E1 only | 8 | | | |
| RAMB18 | 10 | 0 | 210 | 4.76 |
| RAMB18E1 only | 10 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
Both uses the same code, but Spartan/Artix-7 has a worse logic usage in general, specially when taking into account the LUT usage. Has anyone here made similar investigation?