fatimamaz
Newbie level 5
Hello,
I wrote this code for clock division from 921600Hz to 115200Hz, but something is going wrong. Can anyone help me?
I wrote this code for clock division from 921600Hz to 115200Hz, but something is going wrong. Can anyone help me?
Code:
module step1_divider (
input clki,
input reset,
output reg clkf
);
localparam constantNumber = 4'b1000;
reg [3:0] count;
always @ (posedge(clki) or posedge(reset))
begin
if (reset == 1'b1)
begin
count <=4'b0;
clkf <= 1'b0;
end
else
begin
if(count == 4'b0)
clkf <= 1'b1;
if (count == 4'b0100)
clkf <= 1'b0;
if (count == constantNumber)
count <= 4'b0;
count <= count +1;
end
end
endmodule
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