NikosTS
Advanced Member level 4
Hello everyone,
As you can see in the title , i have a problem with a memory that I infer as block RAM but it is implemented as distributed leading to excessive resources being used.
The error showing up in Xilinx XST is the following :
INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features.
The read operation of the RAM is (pretty much ) this one :
If i understand correctly , the tool says that i read from the memory asynchronously but i am pretty sure i do it synchronously. Is there something that i am missing?
Thank you in advance,
Nikos
As you can see in the title , i have a problem with a memory that I infer as block RAM but it is implemented as distributed leading to excessive resources being used.
The error showing up in Xilinx XST is the following :
INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features.
The read operation of the RAM is (pretty much ) this one :
Code Verilog - [expand] 1 2 3 4 5 6 always @(posedge clk) begin if ( counter < 972 ) begin // RAM <banks> has 972 banks of 5 bits each read_reg <= banks[counter][max_error_bits -1 : 0]; counter <= counter + 1; end begin
If i understand correctly , the tool says that i read from the memory asynchronously but i am pretty sure i do it synchronously. Is there something that i am missing?
Thank you in advance,
Nikos
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