Explanation of the latch comparator operation

• Jun 25, 2007

• #1

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arc

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hi...

can anyone give me the operation of latch comparator....???
also how to simulate the design in cadence analog environment....
Please help me out its urgent...

Thanks

 

• Jun 25, 2007

• #2

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mithri

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Re: latch comparator

hi iam attaching some may be useful to u

 

• Jun 25, 2007

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mithri

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Re: latch comparator

hi

 

• Jun 25, 2007

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mithri

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Re: latch comparator

hi,
see this

 

• Jun 25, 2007

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mithri

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Re: latch comparator

hi

 

• Jun 25, 2007

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mithri

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Re: latch comparator

hi

 

• Jun 25, 2007

• #7

G

gevy

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Re: latch comparator

047170055X-2.pdf is content of book only !

 

• Jun 25, 2007

• #8

N

n1cm0c

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Re: latch comparator

Which book ? Could you post the TOC ?

 

• Jun 26, 2007

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arc

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Re: latch comparator

can anyone explain me... how we will decide the value of +Vref and -Vred in pipelined ADC circuit.....please find attachment

 

• Jun 26, 2007

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jerryzhao

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latch comparator

You can compress your figure then attached.
The ADC's reference voltage decide by it's input signal range.

 

• Jun 27, 2007

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arc

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Re: latch comparator

can you please elaborate more... my input signal range is 1.6V p-p...?????

 

• Jun 27, 2007

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jerryzhao

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latch comparator

If there is not PGA(program gain amplifier) adjust your input signal, the reference voltage is 1.6v. +Vref=0.8, -Vref=-0.8 maybe +Vref=Vrp-Vrn, -Vref=Vrn-Vrp.
Example you can design Vrp=0.8, Vrn=0. actual it decided by the common model voltage, usualy, common mode voltage is vdd/2.

 

• Jan 6, 2011

• #13

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anil.rawat

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Re: latch comparator

In differential dynamc latch comparator for pipelined ADC:
Vref is decided by signal range that u want to convert in digital ...i.e in b/w -Vref to +Vref.
which is the signal range of the o/p of opamp in any one stage in PL ADC except last stage.
suppose OPAMP o/p is linearly varying b/w 0.4 V to 1.4 V...then it is 2 V peak to peak differentially.
so here differential signal is varying from -1v(0.4v-1.4v) to +1v(1.4v-0.4v).....(-Vref to +Vref) which is 2v p-p differential.
so for PL ADC, two comparator trip points will be VL(-Vref/4)=-0.25v and VH(+Vref/4)=+0.25V.i.e.
Vin <VL, o/p of comparator =00
VL<Vin<VH, o/p =01
Vin>VH, o/p = 11
where Vin is differential signal varying from -1v to +1v

regards
anil