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Scan chain with mixed clock edge flip-flop

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There is a old IP which used many rising edge and falling edge clock, now it's should be inserted with scan, I want to use the mux to replace all the rising edge clock for falling edge functional clock when on scan mode, and connect all flip-flop together for a high coverage, is it any potential problem about this?
Thanks in advance
 

Hello,

Don't mess up with your clock tree, place the negative-edge-triggered flip-flops first in the scan chain. In this way you can have a mixed chain.

cheers
 

mixed edge is nt advisable i guess!
 

I'll suggest the same as as what ARturi has suggested.

Thats how its done when you have negedge flops along with posedge flops in same clock domain.
 

How long will computer take to complete the scan?
 

My meaning is I have mixed clock tree in functional mode, but we are only one edge clock in scan mode.
 

Does any tools support automatically put negedge flip-flops in front of posedge flip-flops, and at the same time take the timing issue into account.

I think use test_mode to make that negedge flip-flops into posedge ones.
 

Most if not all scan insertion tools will automatically put the negedge flops before the posedge flops in the scan path - but of course, there's nothing the tool can do about scan capture mode, where you still may have negedge flops capturing posedge flop data. So you will lose some fault coverage here, because the negedge flops will always capture 'new' data (the same data that the posedge flop just latched in). To remedy this, you can, if you wish, invert the clocks to the negedge flops during scan mode, but then you're messing with your clock tree, and you don't always want to do that...

John
DFT Digest
 

Sequential ATPG should be helpful in capture mode for the cases when pos edge FF's output being fed into neg edge FF.
 

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