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Slice utilization for Ram in FPGA

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Nikolai

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hello..

i've written the following code for a 64x16 ram..
after synthesis the reports show that the slice utilization is 41%.

Isnt that too much.. Can i minimise the area occupied.?
Im new to constraints, so has it got anything to do with area constraints. ?

Here's the code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Ram_1k is
Port ( addr : in STD_LOGIC_VECTOR (15 downto 0);
sel : in STD_LOGIC;
rw : in STD_LOGIC;
ready : out STD_LOGIC;
data : inout STD_LOGIC_VECTOR (15 downto 0));
end Ram_1k;

architecture Behavioral of Ram_1k is

begin
process(addr,sel,rw)
type t_mem is array (0 to 63) of STD_LOGIC_VECTOR (15 downto 0);
variable mem_data : t_mem :=
("0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000");

begin
data <= "ZZZZZZZZZZZZZZZZ";
ready <= '0';

if sel = '1' then
if rw = '1' then
data <= mem_data(CONV_INTEGER(addr(15 downto 0))) after 1 ns;

ready <= '1';

elsif rw = '0' then
mem_data(CONV_INTEGER(addr(15 downto 0))) := data;
end if;
else
data <= "ZZZZZZZZZZZZZZZZ" after 1 ns;
end if;
end process;
end Behavioral;
 

Synthesis into what type device? If it's a modern Xilinx FPGA with Block RAMs, then remember that Block RAMs are synchronous. Your RAM design needs a clock, otherwise it will synthesize very poorly using the logic fabric.

I assume you are synthesizing using Xilinx ISE XST. You need to write your HDL in a certain way so XST can infer a Block RAM. Refer to the "XST User Guide" chapter "HDL Coding Techniques" section "RAMs and ROMs". It shows VHDL examples.
 

    Nikolai

    Points: 2
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thanx Echo for replying..

the ram was targeted for the XC3s200 fpga by xilinx

and ur right, i havent included the clock in the port list...

since im new to this i copied the code from douglas perry's book and tried to synthesize it...
 

Xilinx FPGA's have many special features that require specific coding techniques. Every new Xilinx designer should read the entire XST manual chapter "HDL Coding Techniques". Another good chapter is "VHDL Language Support" or "Verilog Language Support".

Good luck!
 

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