leongch
Member level 2
Hi guys,
A ) In normal syn FIFO design, the data out is not registered.
assign data_out = MEM[RD_PTR];
B) If we would like to register the data_out as
always @(posedge clk)
data_out <= MEM[RD_PTR];
Compared the method, the B (registered data_out) will read out the data_out 1 clk cycle slower than method A.
In my design I have to design the FIFO with the registered data_out but without the 1clk cycle delay as shown at Method B.
I heard there's some design technics called pre-pop, anyone has any idea of this ? Please advice!
A ) In normal syn FIFO design, the data out is not registered.
assign data_out = MEM[RD_PTR];
B) If we would like to register the data_out as
always @(posedge clk)
data_out <= MEM[RD_PTR];
Compared the method, the B (registered data_out) will read out the data_out 1 clk cycle slower than method A.
In my design I have to design the FIFO with the registered data_out but without the 1clk cycle delay as shown at Method B.
I heard there's some design technics called pre-pop, anyone has any idea of this ? Please advice!