How to simulate this vhdl code using max plus 2

i wanna know how 2 simulate this vhdl file. i'm currenly using max plus 2 v10.2. i have try to simulate the following fil but i cant get the ouput.

here is the brief about what the vhdl code all about.
there is Length which carries 3 bit. when it see the unique Length bit, it will search for the input denote by DataIn_de3, DataIn_de4, DataIn_de5, DataIn_de6, which can receive 3,4,5, and 6 bit respectively.
Once i put it the stimuli, which is anyof DataIn_de, i cant get the output, denote by DAtaOut_de

i hope some1 can help with this. i hope u guys can simualte it using .vec file or if ther is some correction i need to do in the code

forget to attach the file in prvious posting. here is the attachment

i don know why i cant attach the file.anyway i paste the code here


library IEEE;
use IEEE.std_logic_1164.all;

entity huff_dec is
port (
clk : In std_logic;
DataIn_de3 : In std_logic_vector(2 downto 0);
DataIn_de4 : In std_logic_vector(3 downto 0);
DataIn_de5 : In std_logic_vector(4 downto 0);
DataIn_de6 : In std_logic_vector(5 downto 0);

Length : In std_logic_vector(2 downto 0);
DataOut_de : out std_logic_vector(7 downto 0)

);

end huff_dec;

architecture huff_dec_arch of huff_dec is
begin
process(Length)
begin
wait until clk='1';

case Length is
when "010" =>
if (DataIn_de3="111") then
DataOut_de <= "00000000";
end if;

when "011" =>
if (DataIn_de4="1011") then
DataOut_de <= "00000001";
elsif (DataIn_de4="0101") then
DataOut_de <= "00000010";
elsif (DataIn_de4= "0010") then
DataOut_de <= "00000011";
elsif (DataIn_de4= "0001") then
DataOut_de <= "00000100";
end if;

when "100" =>
if (DataIn_de5= "11001") then
DataOut_de <= "00000101";
elsif (DataIn_de5= "10010") then
DataOut_de <= "00000110";
elsif (DataIn_de5= "10001") then
DataOut_de <= "00001000";
elsif (DataIn_de5= "10000") then
DataOut_de <= "00001001";
elsif (DataIn_de5= "01110") then
DataOut_de <= "00000111";
elsif (DataIn_de5= "01101") then
DataOut_de <= "00001010";
elsif (DataIn_de5= "00110") then
DataOut_de <= "00001100";
elsif (DataIn_de5= "01001") then
DataOut_de <= "00001011";
elsif (DataIn_de5= "01000") then
DataOut_de <= "00010000";
elsif (DataIn_de5= "00111") then
DataOut_de <= "00001101";
elsif (DataIn_de5= "00110") then
DataOut_de <= "00001110";
elsif (DataIn_de5= "00001") then
DataOut_de <= "00010001";
elsif (DataIn_de5= "00000") then
DataOut_de <= "00010010";
end if;


when "101" =>
if (DataIn_de6= "110111") then
DataOut_de <= "00010110";
elsif (DataIn_de6= "110110") then
DataOut_de <= "00001111";
elsif (DataIn_de6= "110101") then
DataOut_de <= "00010011";
elsif (DataIn_de6= "110100") then
DataOut_de <= "00011000";
elsif (DataIn_de6= "110001") then
DataOut_de <= "00010100";
elsif (DataIn_de6= "110000") then
DataOut_de <= "00011001";
elsif (DataIn_de6= "101011") then
DataOut_de <= "00011100";
elsif (DataIn_de6= "101010") then
DataOut_de <= "00010101";
elsif (DataIn_de6= "101001") then
DataOut_de <= "00010111";
elsif (DataIn_de6= "101000") then
DataOut_de <= "00011011";
elsif (DataIn_de6= "100111") then
DataOut_de <= "00011101";
elsif (DataIn_de6= "100110") then
DataOut_de <= "00011010";
elsif (DataIn_de6= "011111") then
DataOut_de <= "00011110";
elsif (DataIn_de6= "011110") then
DataOut_de <= "00011111";
end if;
when others =>
DataOut_de <= "--------";

end case;
end process;
end huff_dec_arch;

configuration config_huff_dec of huff_dec is
for huff_dec_arch
end for;
end config_huff_dec;





and this is the .vec file for simulation. i just put the short 1 for testing...but i cant get the result which is DataOut_de

UNIT us; % Keep time in microseconds %
START 0; % Start time %
STOP 80; % Stop time %
INTERVAL 1; % Time between steps %

GROUP CREATE DataOut_de = Encoded7 Encoded6 Encoded5 Encoded4 Encoded3 Encoded2 Encoded1 Encoded0 ;
GROUP CREATE DataIn = |huffman_de:13|UncodeData7.Q |huffman_de:13|UncodeData6.Q |huffman_de:13|UncodeData5.Q |huffman_de:13|UncodeData4.Q |huffman_de:13|UncodeData3.Q |huffman_de:13|UncodeData2.Q |huffman_de:13|UncodeData1.Q |huffman_de:13|UncodeData0.Q ;
INPUTS clk Length\BIN DataIn_de3\BIN DataIn_de4\BIN DataIn_de5\BIN DataIn_de6\BIN; % List of inputs%
OUTPUTS DataOut_de\BIN;

PATTERN
% D D D D %
% L a a a a %
% e T t t t %
% n a a a a %
% c g I I I I %
% l t n n n n %
% k h 3 4 5 6 %

0 0 0 0 0 0
1 011 0 0001 0 0
0 011 0 0001 0 0
1 011 0 0001 0 0
0 011 0 0001 0 0
1 011 0 0001 0 0
0 011 0 0001 0 0
1 011 0 0001 0 0
0 011 0 0001 0 0
1 011 0 0001 0 0
0 011 0 0001 0 0
1 011 0 0001 0 0
0 011 0 0001 0 0
1 011 0 0001 0 0
0 011 0 0001 0 0

;

mcfly said:

i wanna know how 2 simulate this vhdl file. i'm currenly using max plus 2 v10.2. i have try to simulate the following fil but i cant get the ouput.

here is the brief about what the vhdl code all about.
there is Length which carries 3 bit. when it see the unique Length bit, it will search for the input denote by DataIn_de3, DataIn_de4, DataIn_de5, DataIn_de6, which can receive 3,4,5, and 6 bit respectively.
Once i put it the stimuli, which is anyof DataIn_de, i cant get the output, denote by DAtaOut_de

i hope some1 can help with this. i hope u guys can simualte it using .vec file or if ther is some correction i need to do in the code

Click to expand...

I have not used maxplus-II for a long time but I will try to help.
First, you have to be able to compile without any error. I can see one
problem on your code.

wait for clk='1' is usually not synthesizable. You can try to change it
to

if rising_edge (clk) then
.....
end if;

Maxplus-II simulator may get confuse because of that.

I hope that is the problem. Someone else may pick up other mistakes.
Afterall, I only took a quick glance.

Good luck

Gunship