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Problem with code for submodule which generates clocks for other submodules

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doreen105

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I have several submodule in my design.One of them is for generating clocks for other submodules.I have defined generated clocks for other submodules.After synthesize,I found the data buses between different submodules(their clocks are generated by one submodule,and are different) were connected to ground.Why???

Thanks in advance

--Doreen
 

Re: synthesize problem

my code:

wire [15:0] indata;
reg [15:0] outdata;
always @(posedge clk)
if(!rst)
outdata<=0;
else
outdata<=indata;

After synthesize,the outdata[0] connects to constant 0.The RTL compiler said I can" set_attribute optimize_constant_0_flops false " to solve this problem.But it still connects to 0.:cry:
 

Re: synthesize problem

i do work in VHDL n hav lil idea abt verilog....i suppose u r trying to design a 16 bit register

try this code....

Code: 
module pqr (rst, clk, indata, Q);
input rst, clk;
input [15:0] indata;
output [15:0] Q;

reg [15:0] outdata;

always @(posedge clk)
begin
if(!rst)
outdata =0;
else
outdata =indata; 
end
assign Q = outdata;
endmodule

it works as far as i know....(u hav not included rst in the always statement...so i dont know wat it'll design an async or synchronous reset...probably a sync reset ...this is wat i think).....

hey verilog ppl...plz help him out....
 

synthesize problem

Hi,

the design will implement the syncronous reset.i have experience in the verilog.please send me the script file to my email id.r upload some place and send me path.such that i can give u some suggeshion for the improvement.



regards,
ramesh.s.
 

synthesize problem

Hi,

When you run simulation, Is outdata[0] bit always zero?
 

Re: synthesize problem

I am so sorry ,for some reason,I can't mail the whole system code to you.

It is a sample part of the system.

module up(clk,indata,outdata,rst);
input clk,rst;
input [15:0] indata;
output [15:0] outdata;

always @(posedge clk)
if(!rst)
outdata<=0;
else
outdata<=indata;

endmodule

During simulation,the function is right.But after synthesize,in the gate netlist,the outdata[0] connects to constant 0.I am not sure if this is because I have several generated clocks in my design.

Thanks very much.:cry:
 

Re: synthesize problem

Can you try this code?

always @(posedge clk)
if(!rst)
outdata<=16'b0;
else
outdata<=indata;
 

synthesize problem

have a try
always @(posedge clk or negedge rst)
 

Re: synthesize problem

This problem may arise if the LSB of the data bus is not driven high even once.. The synthesis tool may have given a warning stating that data[0] is always '0' and never driven?

To solve this problem i would suggest you tristate the bus when ur not driving the data..like in the reset condition. This should solve the problem.

wire [15:0] indata;
reg [15:0] outdata;
always @(posedge clk)
if(!rst)
outdata<=16'bzzzzzzzzzzzzzzzz;
else
outdata<=indata;
 

synthesize problem

Hi doreen105, The problem may be in some other part of your code that you haven't shown us. Everyone here is guessing, but we may never find it. Maybe you can show us a small complete example that demonstrates the problem, or maybe you can ZIP your Verilog files and upload them here. EDAboard won't allow an attached file with a .v extension.
 

Re: synthesize problem

you can check if the databus's some bits has not been used.


doreen105 said:
I have several submodule in my design.One of them is for generating clocks for other submodules.I have defined generated clocks for other submodules.After synthesize,I found the data buses between different submodules(their clocks are generated by one submodule,and are different) were connected to ground.Why???

Thanks in advance

--Doreen
Click to expand...
 

synthesize problem

Hi,

I think check is this the only logic that is missing in u r design r any other logic also missing. i think some where u constrained u r design reset wrongly other wise the tool will not remove the logic.

Do the formal verification between the rtl and netlist out put if there is any missmatch then we have to think of other wise it is a problem with u r constraints.

regards,
ramesh.s
 

Re: synthesize problem

Or wherever "module up" is instantiated in your system, it's indata[0] bit is
driven by "0" or it might be floating. That could be another reason for your
outdata[0] being tied to 0 after synthesis.

Check the instantiation of module "up".
 

Re: synthesize problem

I have found the problem.Because the next module is an FIR filter,and I use moving and adding instead multiplier,the indata[0] is moved out,never used.

Thanks very much for your help:)

Best regard
Doreen
 

synthesize problem

interesting to knw this prob!! ... how iz shifting different frm multiplying !
 

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