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  1. #1
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    Gate lavel simulation

    Hi Guys

    We understand that whan we have done the Place and route of a design we try to verify its timing by doinf POST LAYOUT timing analysis. Just after the synthesis we also try to verify whether the design is working fine by doing GATE LAVEL simulation. In the FPGA Flow can anyone suggest as to how to go about gate level file. What we get after synthesis is EDIF or EDN file format. How to get a gate lavel file after RTL synthesis so as to verify its functionality with simulation.
    and specially after place and route we get a back annotated file for simulation so second querry is as to how to model the SDF ( Standard delay format) with it to get results in simulation for timing violations.
    Pls specify
    Regards
    Vips

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  2. #2
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    Gate lavel simulation

    After the synthesis u need add EDIF file to ur design, i.e. replace ur RTL file in ur design. And u must copy SDF file to same dir. Then u can run simulation to dynamic verification after scan.
    Above all, just apply for FPGA design.
    Any mistake, plz let me know.Thks.



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  3. #3
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    Gate lavel simulation

    Hi

    Do you mean that an EDIF file with SDF file can be simulated on modelsin?????



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  4. #4
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    Gate lavel simulation

    Hi, vips
    Yes, I do edif sim on modelsim



  5. #5
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    Gate lavel simulation

    better ask such ques in FPGA forum....



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