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initial statements are only used to give some predefined values to a signal @ the start of simulation.
The functionality of initial statements can be done in an FPGA which supports initial value assignment whereas it's not possible in an ASIC
Verilog "initial" statements are fundamentally synthesizable, but a particular tool may not support it for practical reasons. Some FPGA tools support it. I'm guessing that ASIC tools generally don't support it due to some sort of difficulty with automatically instantiating a power-up reset circuit, but that's just my guess.
Yes, you can put delay values into initial blocks, but I see them as two independent synthesis issues. A particular tool might support one feature but not the other.
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