some questiones about hand calculation examples

hi,every one
I have some questiones about ECE 558/658 VLSI Design Principles - Hand

Calculation Examples

Nor Gate Delay Calculation
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1.FALLING and RISING occurs when A↑B=0 and A↓B=0,why? in step 1
2.I think C = CgdnA + CdbnA + CgdnB + CdbnB + CgdpB + CdbpB , in step 3
3.Why double channel length of PMOS?If PMOS saturate,Id dicided by
one MOS,not two? step 7

Hand Calculation Parameters
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1. What is Ls in the table?
2. 0.25um technology,but Lmin=0.24um,why? S/D junctions"side-
diffuse",Lmin=Leffective,right?

thanks!

Here's some thoughts:

1) You need to look for worst case transitions. In a NOR gate, to switch low, worst case is only ONE nmos device pulling low (not two), hence one signal should stay low (while the other rises). If you keep B low, the output sees parasitic capacitance from BOTH pmos devices, hence is the worst case transition.

2) Your thinking is mostly correct, but for the above reasons, if you keep B low the parasitic of both pmos devices must be included.

3) Think of two pmos devices in series. The effect is almost the same as one pmos with doubled length. Even with both transistors in saturation, the effective resistance is doubled. If you're still confused, draw the layout and see how the electrons flow, first through the length of one gate and then through the length of the other.

Parameters: I have no idea what Ls is. In some technologies it refers to the scaling factor on the length. But they should also include a Ws for width scaling.

As for 0.24 um length in 0.25um technology, it's kind of arbitrary, because the technology can use various sizing/scaling parameters to get the final values on silicon.
As for Lmin=Leff, that's incorrect. Lmin is always adjusted, usually by the parameter "ld", but you don't have that one. Ask the professor!