How to find a False path in a design.

Hi Guys

We have been knowing the false path and its nature but i am confused as to how to identify a false path in a design having say 100 modules. We know that false path as defination that it is the path that is never executed or sanitisized henceforth it is not included in the STA . But the million dollar question is if the design is really big the how can one it so as to name it in the synthesis. I want to know the steps followed in the industry. I will value your comments and pls do upload some relevant material or any case study

Thanks in advance
Vips

i will give a simple example.
a path not included for timing calculation is a false path.
u have many options to handle this,like say a reset.
when u set the false path as
set_false_path -through reset
all the paths which occur in the design as reset are considered as false paths other false paths such as combinational loops can be detected through DC(or any)and marked as false paths.

Hi
The question is how to locate the FALSE PATH ... What you answered that once you found the fath /analyzed the path to be false you can DECLARE it by SET_FALSE_PATH key word but the question remains the same how to identify first that the path is a false path ... then to declare it with SET_FALSE_PATH declaration.

HI,

In the first you need's to run the timing analysis tool without setting up the any false paths.then tool will report some violations that are very huge in violation. then you have the path corelate it with the design spec wether you need that path to meet timing r not.then you will get all the false paths.
u r designer will give some false paths load those paths frist other wise you will end up with huge no of violations.


regards,
ramesh.s

You don't necessarily have to identify all possible false paths in the design and turn it off from your timing reports. One way is to just look at your critical paths and address them incrementally. On the other hand, If you are already meeting timing in your design without false path constraints, then you should'nt have to worry about it. However, you can certainly optimize the design better by considering the false paths.

The industry is coming up with tools that auto-generate false paths based on formal techniques. One such product is Conformal Constraint Designer (CCD) that looks at your timing report and proves whether any of your critical paths are false or not. This way the false paths would be turned off on your STA and the resultant SDC's (with additional FPs) can be used to achieve a more optimal design with better timing closure.

Here's a datasheet . . .
https://www.cadence.com/datasheets/encounter_conformal_CD_ds.pdf

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ay

Most SOC designs adopt bus architecture to connect modules. All data traffic are dispatched by bus handler, therefore the timing path between modules are isolated. So once you can manage the false paths inside module and at the module interface, there is nothing to worry. However, if you are talking about paths between different clock domains, you have to take extra care.