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BIP(Bit Interleaved Parity)- VHDL Code

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kuseraj

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bit interleaved parity-8

Hello all,

I want to implement BIP-8 for SONET/SDH( Bit Interleaved Parity) for FPGA.

Anybody is having VHDL code, please inform.

with regards,
rajendra
Code:
 

code for bit interleaved parity

It is very easy.


parity(0) <= data(0) XOR Data(8) XOR Data(16) XOR Data(24) XOR initial(0) ;
parity(1) <= data(1) XOR Data(9) XOR Data(17) XOR Data(25) XOR initial(1);
---

----

parity(7) <= Data(7) xor Data(15) XOR Data(23) XOR Data(31) XOR inital(7);


for next word parity(7 downto 0) will be initial(7 downto 0). So, it continues till end of frame
 

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