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R-S latch simulation question

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pianomania

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rs latch unstable

i use two NOR gate with its output feed into each other as a R-S latch , but why the result is unstable when the simulation step is bigger then 1ns ? what i use is analog simulator.
I mean if we input 0 into S , then the output should be unchanged, but the result will be changed sometimes. But why? it is because the reason of simulator or circuit?
 

latch simulation

Try to use Initial Condition Option and set 1 and 0 (or 0 and 1) for outputs of latch.
 

rs latch instable

gevy said:
Try to use Initial Condition Option and set 1 and 0 (or 0 and 1) for outputs of latch.
Click to expand...

sorry , the unstable condition not happen when it begins but it happen when it is free-running for a few seconds. Its condition is abruptly high when the RS -latch output is still low.
 

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