what is "loop delay"?

" In S-R latch, even a narrow spike or glitch occuring during an active clock phase can set or reset the latch, if the loop delay is shorter than the pulse width"

I quote above the words, in my digital book.

What is the "loop delay"?

Hi ,
As i think loop delays is in sense of Delay which is required to change the state of latch ...if its Nand Gate Latch its reuired 2 Nand gate delay for changing its state and hence loop delay is 2 Nand gate delay ....
If i m wrong correct me..
Regards

loop delay
is like input looped to output

and this is the delay time it takes to feed back thru the gate etc

a loop is a closed circuit of any kind bit like a relay race using battons

if forinstance you use a jam register to program its self

I think loop delay is the time taken by the signal from output terminal to the input terminal as there is feedback in Latch/FF. I am not sure about this please refer to some other text books.

thanks for your kind explain.

but I don't know so far. sorry -_-

if "loop delay" means "delay between Q_bar and R1", Real delay appeared in Q.

see following picture. I ignore gate delay.

Waveform is right?

Even though "loop delay" is longer than pulse width, glitch cause to set or reset the latch output!

text Book tell me like this :

" To illustrate the operation of the clocked SR latch, a sample sequence of CK, S and R waveforms and the correspinding otuput waveform Q are shown in Fig

Note that the circuit is strictly level-sensitive during active clock phases; i.e., any changes occurring in the S and R input voltages when the CK level is equal to "1" will be reflected onto the circuit outputs, Consequently even a narrow spike or glitch occurring during an active clock phase can set or reset the latch, if the loop delay is shorter than the pulse width."

U can't ignore the delay of the gates...

A simple example which gives solution to ur above diagram...

Take a NOR gate and assume that one i/p is ground and other input is at high(say 1.5v) and so the output is at zero... Now u give a zero to the high i/p for a very short time and can u tell me the o/p of that Gate.. u can't say the o/p is high coz it won't reach 1.5v at the o/p ....

If u considered the same thing in the above circuit
then u can easily get why the GLITCH should stay more than the LOOP DELAY.

If u r not clear then feel free to ask me!!