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What should be the depth of my FIFO to prevent underlfow or overrun?

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sudhirkv

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Hi

I have to design a FIFO where SDRAM is running at 50Mhz and LCD controller is also working at 50Mhz. SDRAM can access a data width of 32 bit and LCD can only access 16 bit. Here SDRAM takes 14 cycles for a burst length of 8 to output data. whereas LCD controller can only access one 16 bit in 7 cycles.

So how much depth should be my FIFO for preventing underlfow or over run.

Thanks in advance
 

depth of fifo

depends on your LCD size also, because you need I think you might need two FIFO one is playing another one is loading.
Also depends if you do color space conversion for example from 4:2:2 to RGB.

give more details
 

how to find the depth of a fifo

find the attachement it may be helpful to u
 

fifo design attention

Hi iouri it nothing related with LCD size... am just going to write those datas into the LCD controllers buffer..

This is for Rajesh.. i cant find the attachement.. if possible pls send me to my mail id kvsudhir@gmail.com
 

sdram fifo arbitrierung

two important points should be take attention to when design such a fifo.
first, output data rate of the fifo should match to input data rate,otherwise, the fifo depth will be finate
as the average input data rate is always bigger than
output data rate.
you can use this equation to check whether the fifo
depth is infinite:

(A/B)*W_CLK*w_datawidth=(X/Y) * R_CLK*r_datawidth (1)

w_clk denotes the write clock frequency of fifo
r_clk denotes the read clock frequency of fifo
in write clock domain ,A datas is writen into fifo during B clock cycles.
in read clock domain ,x datas is writen into fifo during y clock cycles.
w_datawidth denotes write data bit width.
A/B means write link bandwidth utilization rate of fifo.
w_CLK*w_datawidth means write link bandwidth .
x/y means write link bandwidth utilization rate of fifo.
r_CLK*r_datawidth means read link bandwidth .
the equation (1) means output data throughput of the fifo should match to input data throughput.

second, the minimum fifo depth.
you can use equation (2) to get your fifo depth.
fifo_depth = burst_length - burst_length * (X/Y) * (r_clk/w_clk) *(r_datawidth/w_datawidth) (2)
make a little change to this equation then you can get :
fifo_depth = burst_length - （burst_length /w_clk)*[r_clk*(x/y)*(r_datawidth/w_datawidth)]
（burst_length /w_clk) means how long time does this write burst keeps.
r_clk*(x/y)*(r_datawidth/w_datawidth) means the actual read rate.
so the product of them means quantity of datas read out during the time when write burst keeps on going into the fifo.
 

fifo altera sdram

can you explain how to cal the fifo's burst_lenth?Thank you


wice said:
two important points should be take attention to when design such a fifo.
first, output data rate of the fifo should match to input data rate,otherwise, the fifo depth will be finate
as the average input data rate is always bigger than
output data rate.
you can use this equation to check whether the fifo
depth is infinite:

(A/B)*W_CLK*w_datawidth=(X/Y) * R_CLK*r_datawidth (1)

w_clk denotes the write clock frequency of fifo
r_clk denotes the read clock frequency of fifo
in write clock domain ,A datas is writen into fifo during B clock cycles.
in read clock domain ,x datas is writen into fifo during y clock cycles.
w_datawidth denotes write data bit width.
A/B means write link bandwidth utilization rate of fifo.
w_CLK*w_datawidth means write link bandwidth .
x/y means write link bandwidth utilization rate of fifo.
r_CLK*r_datawidth means read link bandwidth .
the equation (1) means output data throughput of the fifo should match to input data throughput.

second, the minimum fifo depth.
you can use equation (2) to get your fifo depth.
fifo_depth = burst_length - burst_length * (X/Y) * (r_clk/w_clk) *(r_datawidth/w_datawidth) (2)
make a little change to this equation then you can get :
fifo_depth = burst_length - （burst_length /w_clk)*[r_clk*(x/y)*(r_datawidth/w_datawidth)]
（burst_length /w_clk) means how long time does this write burst keeps.
r_clk*(x/y)*(r_datawidth/w_datawidth) means the actual read rate.
so the product of them means quantity of datas read out during the time when write burst keeps on going into the fifo.
Click to expand...
 

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