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PLL phase noise - for the 74HC4046

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Eugen_E

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74hc4046

I will design a 2nd order PLL based on the 74HC4046, using the type 2 phase comparator. The loop has to multiply 16x the reference frequency.

The reference signal is derived from a quartz crystal, so it has very low phase noise, but the RC VCO inside the 74HC4046 has high phase noise.
From what I read before, the loop bandwidth, to reduce the VCO phase noise, should be as high as possible, so that the VCO tracks well the reference.

Is this correct? And how to estimate the necesary loop bandwidth?


PS: The reference frequency has a couple of values, so I cant generate directly the frequency needed, using a crystal.
 

74hc4046 pll

the PLL act as as high pass filter if the source of the phase noise from the VCO so as the BW increase the phase noise from the VCO will be attenuated , but u willl get the VCO from the reffernce increase as well

so u need to know the phase noise characteristics of ur VCO to be able to calculate the BW

khouly
 

    Eugen_E

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74hc4046 pll design

Thanks for the reply.
I'm interested in a way to estimate the VCO phase noise without a spectrum analyzer, just a rough approximation.
I would rather try different values for bandwidth, but I dont have a spectrum analyzer to verify the results, so if there is another method, please tell me.
The increase in phase noise due to reference multiplication may be tolerable, I just want to reduce as much as I can the VCO noise, which is high for RC VCO.
 

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