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    Verilog <==> VHDL

    I was curious to know if anybody came across a 'decent' software (Not a $15K) ?

    I usually use Verilog, but VHDL even similar a very strange construct sometimes. I am only interested of rtl level not behavioral..

    Regards

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    I think there are a few free simulator available. Check this out:
    www.verilog.net/free.html



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  3. #3
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    check elektoda i think that i have seen some verilog and VHDL converter, if u dodn't find then tell me.



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    you may check X-HDL, it's a good biidirectional translator: http://www.ids4eda.com/xhdl.htm



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    Re: Verilog <==> VHDL

    how to use th tool?



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    X-HDL is the best tool in this area .
    The problem is that it is not free , but not so expensive also ...



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    i think it is the best way to rewrite it in the other language.
    if you know the structure of design , you will implement it easier.



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    Re: Verilog <==> VHDL

    xhdl is cheap and easy to use but it does not do good job when it comes to converting behavioral code or converting new constructs in verilog 2000 and beyond. Overall it converts about 80% of your code and you have to do the rest by hand.



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    Verilog <==> VHDL

    I dont think there is any difference on the schematic.Why convert from one to the other?



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  10. #10
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    Verilog <==> VHDL

    i don't think it's a good idea to translate verilog & vhdl each other. if you have both model of them, try modlesim, ncsim or vcsmx to verification.
    xhdl is good tool, but i still think that isn't good way.
    you can read it into dc & write out with another format, but it's gtech_lib based.



  11. #11
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    Re: Verilog <==> VHDL

    we got blocking statement in verilog, but no such statement analog to
    VHDL? I wonder it can translate it well.



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