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  1. #1
    Junior Member level 3
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    FSM using min hardware very urgent

    Output is asserted 1 if
    pattern 101 is detected in last 4 inputs.


    Eg: I/P 0 1 0 1 0 0 1 1 0 1 0 1 0
    O/P 0 0 0 1 1 0 0 0 0 1 1 1 1

    i am done with the state diagram(7 states ) n using D-Flip Flops...but for giving the inputs to the DFF's i got 3 equations ..as i hav to use min harware i am planning to implement the equations using PLA(programmable logic array) r PAL...but i hav to write verilog code for the above design n test it....

    WILL IT BE POSSIBLE TO WRITE VERILOG CODE FOR THE PLA R PAL I USE r is there any other way i can reduce the hardware (for the input equations of DFF's)

    plzz respond its very urgent
    thnx in advance

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  2. #2
    Advanced Member level 5
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    FSM using min hardware very urgent

    One common method is to translate your state machine into a 'case' statement, and then let the synthesizer software do the tedious logic minimization. It's usually very good at doing that.

    Or, since you already have the three equations, you can simply put them into your Verilog, and the synthesizer software should automatically minimize them for you.



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