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There are two methods used for verifying a design against a standard.
1. Formal verification or equivalence testing uses a tool, such as Synopsys Formality, to test the design in one form such as the RTL description which is known to be functionally valid against a second form such as the gate description to ensure fidelity. The comparison is made by testing for logical equivalency.
2. Dynamic verification tests the design function by comparing its behavior with the specification using simulation.
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