khsung
Newbie level 3
how to reduce phase noise
I am designing a VCO using the voltage-to-current converter as shown in the Fig.13 of "A PLL Clock generator with 5 to 110MHz of lock range for microprocessors" JSSC. 1992 Nov.
Phase noise simulation(PSS, Pnoise) results shows the main noise source is the voltage-to-current converter NMOS and PMOS(drain-source resistance thermal noise).
how can I reduce the phase noise?
Thank you.
I am designing a VCO using the voltage-to-current converter as shown in the Fig.13 of "A PLL Clock generator with 5 to 110MHz of lock range for microprocessors" JSSC. 1992 Nov.
Phase noise simulation(PSS, Pnoise) results shows the main noise source is the voltage-to-current converter NMOS and PMOS(drain-source resistance thermal noise).
how can I reduce the phase noise?
Thank you.