A problem about mapping the verilog-netlist to spice-netlist

Hello ,everyone:

I try to translant the verilog-beharioral netlist into spice-netlist using synopsys hercules.

The whole command is as follows:

nettran -verilog ../vlog/file.v -verilog-b0 VSS -verilog-b1 VDD
-cdl /export/DE_home1/caslib/smic/aci/sc-m/lvs_netlist/smic18m.cdl
-outType spice -outName file.spi


In this command, I've to use the artisan library "smic18m.cdl", then the problem come out.

The syntax in the smic18m.cdl seem to be different from the standard spice , as the following:

.subckt DFFHQNX2M QN CK D
M0 cn c net52 VDD P w=0.8u l=0.18u m=1 $name=/t7
M1 net58 c VDD VDD P w=0.42u l=0.18u m=1 $name=/t5
M2 pm net110 net58 VDD P w=0.42u l=0.18u m=1 $name=/t20
M3 net64 s VDD VDD P w=0.22u l=0.18u m=1 $name=/t18
M4 net101 c net64 VDD P w=0.22u l=0.18u m=1 $name=/t17
M5 net70 m VDD VDD P w=0.42u l=0.18u m=1 $name=/t14
......

And after the translation , the output spice-netlist is different from the spice syntax too , as the folloing:

.SUBCKT XOR3XLM Y A B C
+
M19 Y net54 VSS VSS N NAME='(g1/n)' M=1 L=0.18u W=0.28u
M18 VDD net54 Y VDD P NAME='(g1/p)' M=1 L=0.18u W=0.56u
M17 net69 nmin1 VSS VSS N NAME='(g2/n)' M=1 L=0.18u W=0.42u
M16 VDD nmin1 net69 VDD P NAME='(g2/p)' M=1 L=0.18u W=0.73u

So when I use this spice-netlist in the mix-signal simulation using NS-VCS,it pop up warnings saying the instances

are not recognized :

WARNING:0x20201112:Instance, 'm18', has unsupported instance parameter,
'name', at line 10 in file '/export/DE_home1/wangmm/project/
alice/sim/mix_sim/module_test/netlist/adder.spi'. It is ignored

I hope someone may give me some hints, I really don't know how to solve this problem , and the ARM suport in China

can't give me help too, so I really really hope to get an answer here.

Thank you in advance!

write a perl code to erase the 6th column of each line when 5th column = P or N ;