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how to simulate CMOS op amp?

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ridzu

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simulate cmos

i have a problem to simulate the low voltage op amp i have design. can someone give brief description on how to simulate this op amp (i use cadence spectre).
 

ridzu said:
i have a problem to simulate the low voltage op amp i have design. can someone give brief description on how to simulate this op amp (i use cadence spectre).
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hi,
plz have a read p.e allen's book, in which i think there are some good example to simulate a op-amp with spice.
good luck
jeff
 

i already read that book. i looking for a more detail explanation than that. i am new in this field.

Added after 2 hours 11 minutes:

can anyone explain to me what is the difference btw NMOS and NMOS4 in cadencle library
 

Hi Ridzu,

NMOS and NMOS4 are naming difference. Around the industry, normally we specify NMOS with bulk connection to VDD/GND (PMOS/NMOS). The symbol is 3-terminal device. As for NMOS4 (4-terminal device), we can choose to connect bulk to VDD/GND or to the source(NMOS case). Either way depending on application.
 

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