Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Multifinger v/s Single wide transistor

Status
Not open for further replies.
ryusgnal

ryusgnal

Advanced Member level 4
Joined
Oct 4, 2005
Messages
102
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,298
Location
Malaysia
Activity points
1,992
when to use multifinger transistor layout

which one is better, Multifinger transistor or single wide transistor? Why? Anyone have any reference?
 

multi finger layout capacitance

hi
i think multi fingure is better than single wide
bcs in multi figure layout u can acheive good matching
for more information you can refer the following link
**broken link removed**
regards
analayout
 

multi finger transistor

Not only matching may be better in multifinger layout. Also some parasitic capacitances, resistances.
a.
 

many processes give the unit wide limit, if your single wide is longer than the limit, there may be process degrade
 

Multifinger minimizes paracitic capacitances as well paracitic resistance etc. It can also provide better matching - but this is not the best matching method. You can use multifinger together with cross quad or centroid structures to achieve better matching of the devices.

In order to fully comprehent this draw down a single and a multifinger of 3µm n-MOS

Now check paracitics.
Check in which device technology variations are significant and where they are cancelled.

D.
 

Wait a second. Multi-finger layout is not necessarily reducing parasitic capacitance. It reduces parasitic resistance ONLY.

For example, if your PMOS transistor is 100u/1u, then you split them into 2 finger and make them in parallel, you reduce the parasitic resistance by a factor of 4 since you cut it into 50u/1u and parallelize it. However, what about parasitic capacitance?
The gate oxide capacitance does not reduce, it is the same. The gate overlap capacitance to drain/source on the other hand is increased as you have more overlap chances since you have more dimensions now.

Added after 47 seconds:

Check with p.93 on "IC Mask Layout", essential layout techniques
 

Yes, on the christopher's two excellent books on mask design,that the parasitic cap is not reduced in the multifinger config.
 

One more thing, multi-finger layout is NOT necessarily for matching.
If you have just ONE single transistor, you need not do matching. Then should we use multi-finger layout?
if you don't need to reduce parasitic resistance, I'd recommended you draw a WHOLE BIG transistor and it is better. Photomask misalignment is an absolute value. Say the photomask always mis-align by 0.1um. If you have one single transistor, then say 10um, your final width is 9.9um. if you have 4 multi-finger transistor of each 2.5um, then you mis-align each by 0.1um, then the final mis-align is 0.1x4=0.4um, which is a lot larger than a WHOLE BIG transistor. So, when u design or decide the layout, be sure you understand the backend first
 
  • Like
Reactions: izatxamir

    ryusgnal

    ryusgnal

    Points: 2
    Helpful Answer Positive Rating
    I

    izatxamir

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top