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Case error LOC when converting VHDL to Verilog

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urakiki

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Hi,
I am new to VHDL. And I try to convert to verilog.
--
signal internalCNT, CNTupto, internalCNTaddr: std_logic_vector(11 downto 0);
type errorLOCtype is array (7 downto 0) of std_logic_vector(7 downto 0);
signal errorLOC: errorLOCtype;
........
........
.....
case errorLOC(conv_integer(internalCNT(1 downto 0) & '0'))(2 downto 0) is ???

What the case mean?? How the verilog look like for the case statement?
Thanks
 

vhdl conv_integer

which tool u r using ???
 

vhdl conv_integer verilog

I think it would be better if you can post your codes here. Difficult to debug if we simply guessing.
 

conv_integer in verilog

urakiki said:
Hi,
I am new to VHDL. And I try to convert to verilog.
--
signal internalCNT, CNTupto, internalCNTaddr: std_logic_vector(11 downto 0);
type errorLOCtype is array (7 downto 0) of std_logic_vector(7 downto 0);
signal errorLOC: errorLOCtype;
........
........
.....
case errorLOC(conv_integer(internalCNT(1 downto 0) & '0'))(2 downto 0) is ???

What the case mean?? How the verilog look like for the case statement?
Thanks
Click to expand...

case errorLOC(index1)(index2)
ur index1 in vhdl is conv_integer(internalCNT(1 downto 0) & '0')
in verilog it should be the same but no need to convert to integer. and "& 0".....I think ur appending 0.....Long back I worked in VHDL............."& 0" means........multiply with 2 in decimal format......
u can do it in verilog simply by {.....,1'b1} .........

index2 is simple....

U dont need to go for user defined data type in verilog.
2d arrays r available in verilog....use them.......

Added after 1 minutes:

2d array format....

reg no_of_bits_in_vector variable_name no_of_vectors
 

verilog 2d array

"HDL Chip Design" has both code in VHDL and Verilog for each example
You can download this book in forum Ebooks
 

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