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hi i need help in implementation of fpga

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hi iam doing project on implementation of five variable logic function using fpga's configurable logic block in verilog hdl. can any one explain me how to implement and how to write the code for implementation of five variable logic function in fpga's clb.
 

Can you describe your design in detail?
 

hi! i am implementing a logic function from o/p of the clb. In the architecture of fpga there are logic blocks ,connection matrices ,i/o blocks. In logic block there are three function generators(LUTs) with first two LUTs having i/ps F(1:4),G(1:4),and o/ps are F' and G'.These o/ps and another i/p variable H1 are given as the i/ps of third LUT.The o/p of third LUT is given to the muxs and o/ps of muxes are given to the d flipflops.Thesed flipflops will give the o/ps such as yq and xq . to get this we need to program above elements .
I dont know about programming and also veilog code for implementing the function. please can any one explain me
 

can any one help me in implementation of logic function using fpga's clb
 

I didn't understand, how your application work, but the best is to try to see if you the xilinx on the documentation of your ISE if you use it.I ll be hapy to work with you, I m on design of mod/demo on fpga..............................MOC.........................thanx
 

Hi,
I know a little bit on FPGA (Xilinx Spartan3 XC3S200 FT256 -5) and I use VHDL to program, but actually I couldn't understand what you mean. If you just give the idea of your project and a little description so I will do my best helping you.
 

now i am sending the structure of clb. In that structure iam giving inputs through g1,g2,g3,g4 and f1,f2,f3,f4 to the luts(function generatora) . after the implementation of luts o/ps of luts are feed into another three input.In this one we are using another variable (say h1).like that the implementation can be done and yhe o/ps taken at the dffs and at x and y.

now iam using spartan 2e clb which is having four slices .if possible give can any one explain me how 16:1 lut can be implemented and also the code
for implementation of 6 varible function . i want urgently
 

Do you have a specific need to understand the detailed workings of the CLB? That's a lot to learn - every device family is different. It's much easier to describe your logic function in HDL (VHDL or Verilog), and then let the synthesis software worry about the implementation details. The tools know how to combine multiple CLB into larger functions, and how to optimize placement and routing for best speed or minimum area.

What do you mean by "16:1 LUT"? If you mean 16 inputs and one output, then a general solution is a 65536 bit ROM. Of course, many 16-input functions can be simplified through logic minimization.

A 6-variable function could require a 64-bit LUT (you could combine four Xilinx 16-bit LUTs). However, many 6-variable functions can be simplified through boolean minimization, and may fit into some combination of smaller LUTs. The synthesis software will figure that out for you.
 

thnx alot guyzz for ur support...
i'm also using VHDL for programming but presently stuck with sum of the codes..
i've basic knowledge of vhdl..so can anyone help me with codes of LED blinking, adder, counter, and serial communication
 

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