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Well....
in your Core Ring, you should have VDD and VSS rectangular route.
Beside that, you should manually insert Power and Ground pad to the disign that will connect to the VDD and VSS at your Core Ring.
For the power and ground pad, the VDD should be connect to the portion for VDD for Pad rign internally.
While for the gnd pad will do the same as well.
After that, run the Pad Ring function, or place in FillerPad to connect all the VDD and GND for the Chip.
I am follow this method. My design is core limit, due to reduce area that some core power ring and pad power ring be placed same area.
I want to connect both power ring. I don't know this method disadvantage.
It depends on your switching frequency, how many digital output, if they are switching at the same time ...
The worst is a bus switching at the same time .... very very noisy !!!
You could have no core POWER ring.
Switching noise is determinated by IO power ring, Don't forget--In the IO
PAD ring, have two power ring, one IO power ring,the other is VDD power
ring that same as core power ring.
You could have no core POWER ring.
Switching noise is determinated by IO power ring, Don't forget--In the IO
PAD ring, have two power ring, one IO power ring,the other is VDD power
ring that same as core power ring.
It looks like you met the area problem. Basically, okguy's idea are all right. Sometimes, I merged the ground ring to save the area, but tried not to merge the analog/pad/core power together. Double bound to alleivate the problem, if core limited...
Estimated from the date you posted this mail, I believed you should have your chip back. Could we share your experiences?
It depends on your application.
The best method is to seperate the power/gnd rails of IO and core if area and pad number aren't constrained. In my previos design, i had merged the power/gnd IO rail with the internal digital core power/gnd rail due to pad number constrain. But the analog portion still has its own power/gnd rail to prevent noise coupling. Because the IO will generate large noise on the power/gnd rail, and that will affect the setup/hold time of the digital ckt. It's better to reserve more timing margin during synthesis to cover this effect.
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