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    sv assertions

    hi

    I know the basics of SV. I am having a doubt, is it enough to learn SV ASSERTIONS to do a complete full project (verifying) or should i learn the whole SV like classes, interfaces, random constraints and so on.

    thanks in advance

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    systemverilog assertion class

    Quote Originally Posted by krishna_1980
    hi

    I know the basics of SV. I am having a doubt, is it enough to learn SV ASSERTIONS to do a complete full project (verifying) or should i learn the whole SV like classes, interfaces, random constraints and so on.

    thanks in advance
    Hi Krishna,
    Depends on what your primary role is - are you a RTL designer doing some verification or Verif engineer? The reason I ask that is, learning class and associated good practices will take time and usually RTL engineers won't have that luxury of learning it all in one go. As you said you are already familiar with SVA, that's a good sweet spot for RTL guys to start with and if your company has formal tools, that's a great way to test your modules without testbenches (We showed that in our SVA & PSL books).

    (Now a plug-in from my company side):

    As we have seen this with several companies, I have put together a set of slides that would exactly address this problem - "Incremental Adoption of SystemVerilog". I would be glad to come and deliver it at your company say for 1 hour or so (free of cost). Let me know if you are based in Bangalore and are interested via email at ajeetha <> gmail.com

    HTH
    Ajeetha, CVC
    www.noveldv.com


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    sv +assertions

    Dear Ajeetha,

    I am not working in any comp. i want to know is it possible to verify a project completely by using only SVA'S.



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    assertions in sv classes

    Assertions should use with respect you RTL code .
    Suppose you have some failures in overall verification.
    If you have FIFO's in design, may be the failures because of overflow and underflow
    These assertions will be useful to find out where the exact problem



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    Re: systemverilog assertions

    SVA is only used to very simpler designs than complex ones... The reason being that, for complex designs => more states => more simulation runs



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    Re: systemverilog assertions

    Can anybody of u explain what do u mean by verifying RTL without testbenches

    i am suppose to do a project using SVA

    Can anybody list the must reads before i start



    regards
    natg



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    Re: systemverilog assertions

    To do complete verification you should have a complete test bench and employ the class features of sv as needed. Simple duts do not require something like a class for verification. Assertions are good to verify protocol type design features. Incorporating assertions in your dut code and adding them in your test bench help simplify the complexity of any given test for your dut. Use assertions as needed. Again, sv assertions are great to verify protocol (need ack after 3 clock cycles after req, verify this with an assertion). However, using classes and providing constrained random stimulus is a good way to verify your design. SVA is a simply a tool to help verify your design and should not be used alone to verify a design.



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    Re: systemverilog assertions

    I think SVA can help designer to check its DUT more efficiently , so the basic usage should be learned!



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