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I have 2 years of VIM experience in Verilog design.
But when I met with EMACS with verilog-mode, I changed to emacs since then. Emacs gives me the most flexibility in edit. and verilog-mode save me so much time in verilog hierarchy instantiations.
But I confess that, emacs is more difficult than anything else. the learning curve is comparatively long.
If you have solid programing background especially functional programing basis. I suggest emacs with verilog-mode. Otherwise, use vim or else.
Please don't make such comments unless you know what is it.
Learning emacs is like learning to drive a car, hard to learn but
becomes as easy as reflexes once you know how to do it.
The features of emacs.. They are incomparable with other..
I'll post a new topic on some useful tricks of emacs for vlsi
engineers that i learned from my experience.
There is a nice book from o-reilly "GNU emacs" in nutshell series..
However it does have much info about VHDL or verilog mode.
below are some references you can use....
but if you really want to learn emacs the best way is use it often.
Well there is another editor i found good..."Simplifide"
which is a eclipse bases plug in.
Its still in development but still quit useful.
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