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Metal 1 parallel with Poly gate to decrease resistance

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jagadeesh2k1

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Hi in analog layout over the poly gate metal 1 is placed so that the overall resistance is decresed is it a good practice.

One more thing is that any signal lines be routed over active region.
 

I'm having trouble picturing metal 1 // poly to reduce resistance. Are you viaing down to poly from metal 1 to decrease the overall series resistance or is metal 1 just running above it without any electrical connection to poly?

It is not recommended to run signal lines over active. If you do make sure the active area is not critical in the sense that any signal noise that may get coupled into your active area will cause problems else where in your circuit.
 

Other than signal line over poly gate. Most of the proces don't allow open metal to poly contact over active area. Btw, the poly gate usually have low enough resistance. The most important is the poly gate capacitance
 

It is only good if you have long enough POLY lines, so the POLY two ends can be turned on at almost the same time by METAL connection. This is especially helpful in some buffer design layout
 

hung_wai_ming(at)hotmail.com said:
It is only good if you have long enough POLY lines, so the POLY two ends can be turned on at almost the same time by METAL connection. This is especially helpful in some buffer design layout
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hi,hungwaiming,it is said metal on poly or diffusion would cause potential problem like etch and parastic transistor,and you can't get a clean DRC,so how do your make sure ur trick wont bring reliable problems?THX
Can you give a layout example?

SEE for potential problem
 

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