+ Post New Thread
Results 1 to 12 of 12

7th February 2007, 18:15 #1
 Join Date
 Feb 2006
 Posts
 64
 Helped
 3 / 3
 Points
 1,622
 Level
 9
RFIC design question
I am currently designing a LNA by using Si with 0.18um technology. My target is to design an LNA that has NF < 2db, Gain =15db and OIP3 >3, I<4mA.
I am using a LC folded inductor source degeneration topology. Below are some of my questions:
1. Does folded technique will provide better noise performance than cascode technique?
2. I get a gain of 50dB for my design(i know it is wrong...:)), could i know what went wrong with my circuit?
3. Any idea how to improve NF of LNA?
4. Does adding a capacitor at GateSource terminal at first stage NMOS will help to reduce the NF (especially gate induced noise)?
Thank you in advance.

7th February 2007, 19:17 #2
 Join Date
 Oct 2001
 Posts
 4,646
 Helped
 1360 / 1360
 Points
 32,478
 Level
 44
Re: RFIC design question
There are no big differences in RF performances between cascode and folded cascode structures, but folded cascode allows for lower voltage operation.
Noise figure improves by minimizing the size of the input device.
50dB of gain means that your LNA is not DC supplied.

7th February 2007, 19:17

8th February 2007, 04:06 #3
RFIC design question
4: the parallel cap helps to increase the Cgs, the resonate Lg, the input Q, then improve the NF
comments of "There are no big differences in RF performances between cascode and folded cascode structures, but folded cascode allows for lower voltage operation. " is right, the power is doubled then.

8th February 2007, 20:21 #4
 Join Date
 Feb 2006
 Posts
 64
 Helped
 3 / 3
 Points
 1,622
 Level
 9
Re: RFIC design question
[quote="neo"]4: the parallel cap helps to increase the Cgs, the resonate Lg, the input Q, then improve the NF
Neo, could you explain further about how the parallel cap helps to improve NF? How is it relate to Lg and Q?
By the way could you provide any formula or intuition way to prove this?
Thanks!!

8th February 2007, 20:21

8th February 2007, 21:49 #5
 Join Date
 May 2005
 Posts
 78
 Helped
 4 / 4
 Points
 1,722
 Level
 9
Re: RFIC design question
[quote="electronics_sky"]
Originally Posted by neoOriginally Posted by neo
to your question, the gateinduced noise is never the dominant noise source in LNA design, it is proportional to Cgs^2 and Cgs is mainly some tens of femto farads, therefore you can imagine what the impact of gate induced noise is.
15 dB gain and 2 dB noise figure should be easily achieved in 0.18 um process.

8th February 2007, 21:49

9th February 2007, 04:13 #6
 Join Date
 Feb 2006
 Posts
 64
 Helped
 3 / 3
 Points
 1,622
 Level
 9
RFIC design question
Hi estradasphere, How about if i only need a very narrowband (2.11G2.17Ghz, BW = 60Mhz)?
I know Channel noise of first stage transistor is the dominat in LNA design, however if we ignore the gate induced noise in our calculation then it will become dominant. Therefore we need to add a capacitance to gatesource inorder to decouple the Q of first stage transistor in order to help reduce the gate induced noise.
By the way, what are your suggestion to improve the NF of a cascode LNA instead of add a capacitance to gatesource?
As for the cascode topology, i am thinking of using a inductor load to decrease the parasitic capacitance of second stage PMOS, Cgs. Anybody think this will help to improve the NF as well?
As i know, with the smaller channel length we will have better NF, could i know any formula will prove this? If we have a same W/L ratio from 0.18um process and 0.5um process which one will provide smaller NF?
Please comment and correct me if i am wrong.
Thanks

9th February 2007, 04:22 #7
RFIC design question
electronics_sky, u can refered to "CMOS LowNoise Amplifier Design Optimization Techniques", it may help.
If u control the input Q not to high, it will meet ur
matching requirement.
And the process variations, the input transistor itself will suffer from the corners, right?
But frankly speaking, estradasphere, i donnot like the adding Cgs neither, anyway, it is not a generic approach.

9th February 2007, 04:28 #8
 Join Date
 Feb 2006
 Posts
 64
 Helped
 3 / 3
 Points
 1,622
 Level
 9
RFIC design question
Hi Neo, i am currently refered to "CMOS LowNoise Amplifier Design Optimization Techniques", but i found that its approach is quite different as what was discussed by Thomas H. Lee in his "1.5v, 1.5Ghz LNA for GPS".
I am sorry, i don't understand what you mean by "And the process variations, the input transistor itself will suffer from the corners, right?"

10th February 2007, 20:11 #9
 Join Date
 Jul 2006
 Posts
 150
 Helped
 13 / 13
 Points
 2,833
 Level
 12
Re: RFIC design question
Can you give an article which describes the LC fold technique ? (I dont mean to Folded cascode...but the LCFold technique).
B.R

11th February 2007, 13:03 #10
 Join Date
 May 2005
 Posts
 78
 Helped
 4 / 4
 Points
 1,722
 Level
 9
Re: RFIC design question
[quote="electronics_sky"]Hi estradasphere, How about if i only need a very narrowband (2.11G2.17Ghz, BW = 60Mhz)?
hi,
if you want to make an "onchip" narrowband matching, then it is more critical, because you have to realize your input match exactly at 2.1 GHz (if you intend to make an offchip matching with a package, then this is no more critical). i would run a simple sparameter montecarlo simulation (takes maybe 20 minutes) and see the variation of the input match. the lna should be as simple as possible and i would avoid to use too many elements in my circuit.
to your question; in my opinion, keeping the W/L ratio constant, the circuit with the smaller L would give the smallest NF, because, you get the same gain with less transistors, which means less noise and less parasitics. please correct me, if i'm wrong.

13th February 2007, 07:43 #11
 Join Date
 May 2005
 Posts
 172
 Helped
 15 / 15
 Points
 2,376
 Level
 11
RFIC design question
I do not agree with both estradasphere and neo. Actually, the C, which parallel to Cgs, will decrease the input side Q (check with Lee). The Q will affect NF, linearity of the LNA performance. The higher Q, the smaller NF. As to the paper "CMOS LowNoise Amplifier Design Optimization Techniques", there is a mistake there. When the parallel C added, the effective wt will be changed to gm/(Cgs+C), it is not convention wt any more. It means it will degrade the NF at the same bias current. The equation (26) will not be valid.

13th February 2007, 07:43

18th February 2007, 12:47 #12
 Join Date
 May 2005
 Posts
 78
 Helped
 4 / 4
 Points
 1,722
 Level
 9
Re: RFIC design question
Originally Posted by noiseless
your theoretical point of view may be correct. maybe you'll get 0.2 dB lower noise figure with parallel C or maybe a little bit lower? but the main problem is the robustness of your design despite several process variations. a high input Q might be good for noise figure, but quite risky in terms of onchip input matching (again, process variation) and stability of your lna, the input Q of cmos transistors in commonsource topology is high enough even without adding any capacitances in parallel.
+ Post New Thread
Please login