why setup and hold times are there in digiatl circuits?

Can anyone tell me how setup time and hold time come into picture of digital ciruits ( in flioflops and latches)???

I heard the consequences of setup and hold time violations... But I want exact reason for this timings....


thanx in advance

Hi tumma,
You need to consult ur colegues, are also start from wakerly

Flipflops are feedback circuits.
They are amplifiers.....
They will sample input signal and it will amplify.
The input signal is not allways 0 or 1....
There is rising edge and falling edge also......

If the FF is sampling when there is rising r falling......
...it may sample 2.4 v r 2.6 v........insted of 0v r 5v......

then it takes more time for this amplifier to amplify this 2.4 r 2.6v signal to 0 r 5 v

and we canot decide what it is sampling...2.4 r 2.6.......which results 0 r 1 after some time

so from the above we can not say the out put is 0 r 1
and the time it takes to show 1 r 0.....

this inability is called metastability......

Y a signal is hving rising r falling edge???just coz of capactiences....

I think u are able to figure out some thing.....

ankith .. what expalination u have given works for setup time ... what about hold time?

sivakumar_tumma,
Setup time restrictions are due to the inability of an input circuit to respond instantaneously to a change in input. Setup time allows the input circuit to settle out before the clock edge accurs.
.
Hold time restrictions are due to the inability of the input circuit to respond to the positive feedbak from the output that ensures that the output will remain in a stable state. Some off the shelf devices have a minimum hold time of 0.
Regards,
Kral

Hi sivakumar_tumma

For hold time........

when the FF samples the data........this data enters the loop....
FF needs some time to allow this data to pass through the whole loop path...........then only this new sampled data can over right the previous one.......and this loop has new data to amplifi........

If data changes in hold period.......
then the data that enters the loop is chaged.......so the whole loop is not able to decide what to amplify........
this iinability is called race condition.......

i think im not going in right way.....

karal,
thank u very much .. ur explanation gave me the insight .........