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If you search the Xilinx or Altera webistes, you will find info on PCI Arbiters. Else search the EDA board for PCI Specification sheets.. In this spec sheet there is a chapter detailing the Arbiter signals and operation.
The arbiter determines if the BUS is busy by using the FRAME and IRDY signals. IF the bus is free, it checks the REQ lines to see which master has requested the bus and assigns the GNT accordingly. If the bus is busy, it deasserts the GNT for the current master and gives GNT for the next. BUS control is transferred to the next master when the current master finishes its transfer.
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